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ASIC RTL Design Engineer, Machine Learning Accelerators at Google

Location: Madison, WI, WI, 53701, US

Job Summary:

Job Duties and Scopes:
- Define micro-architecture specifications and own implementation of Register-Transfer Level (RTL).
- Create test benches and debug complex logic simulations.
- Achieve functionality and power, performance, and area (PPA) closure.
- Collaborate with software teams to ensure successful solutions and contribute to design methodology and code reviews.

Required Skills:
- Proficiency in logic design and silicon-based ICs/chips development.
- Understanding of computer architecture and memory subsystem architecture.
- Familiarity with engineering best practices (code reviews, testing, refactoring).
- Knowledge of computer networks and machine learning concepts.

Required Experiences:
- Bachelor's degree in relevant fields or equivalent practical experience.
- 2 years of experience with industry-standard tools and methodologies in silicon development.
- Preferred: 7 years of experience in ASIC design and successful ASIC product development.

Job URLs: