Location: Santa Clara, CA, 95051, US
Job Summary:
Job Duties:
- Lead RTL to GDS design process.
- Address timing and power challenges.
- Conduct physical verification before tape-out.
- Set up and automate physical design processes.
- Collaborate on custom logic and IP integration.
Required Skills (Keywords):
- EDA tools: Fusion Compiler, IC Compiler II, etc.
- Floorplanning, placement, routing, timing closure.
- CTS optimizations, clock routing, cell placement.
- Physical verification: DRC, LVS, ERC.
- Low-power design techniques.
- Scripting languages: Tcl, Perl, Python.
- Communication and teamwork.
Required Experience (Topics):
- BS/MS in Electrical Engineering or Computer Science.
- 3-12 years of relevant experience.
- Successful tape-out track record.
- Familiarity with advanced FinFET technology nodes.
Job URLs: